integrated circuit systems, inc. general description features ics9177 block diagram ics9177revb060297p high frequency system clock generator the ics9177 is a multiple output clock generator ideal for high speed processor system applications. a single high- speed internal vco is utilized to derive up to four simultaneous clock output frequencies. this enables output clock skew matching and the minimization of clock jitter. the internal vco operates up to 350 mhz providing edge skew matched output clocks. one differential pecl (positive ecl) output pair provides a high speed processor clock. 12 ttl clock outputs are also provided for other system functions, such as bus clocks. input selection pins are used to select the ttl output clock frequencies. for information about ics9177 customization optics, please contact ics. ? provides output frequencies up to 175 mhz ? internal vco is divided into four skew-matched output frequencies (out a, b, c, d) ? external clock feedback provides input to output skew matching ? differential pecl clock output pair provided for high speed output (out a) ? 12 ttl clock outputs (for out b, c, d) ? single 5 volt power supply voltage ? internal loop filters ? 52-pin qfp package pin configuration 52-pin qfp ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9177 pin description *internal pull-up resistor pin num- ber pin name type description 1 gnd 2 refclk input from external oscillator 3 fbclk input external pll feedback path from one of the outc outputs 4 dsel1# input pll divider mode control (contains internal pull-up resistors) 5 dsel0# input 6 testen input test mode enable pin 7 tstclk input external test clk 8nc 9vcc 10 gnd 11 pcout1 output ttl - gr oup 2 programmable clock outputs 12 pcout0 output 13 gnd 14 vcc 15 pbout1 output ttl - gr oup 1 programmable clock outputs 16 pbout0 output 17 vcc 18 gnd 19 paout1 output ttl - gr oup 0 programmable clock outputs 20 paout0 output 21 vcc 22 gnd 23 resetl input low true divider reset pin 24 bout1 output ttl - 50 mhz output clock 25 bout0 output 26 vcc 27 gnd pin num- ber pin name type description 28 cout2 output ttl - 25 mhz output clock 29 cout1 output 30 vcc 31 gnd 32 cout0 ttl - 25 mhz output clock 33 dout0 ttl - 12.5 mhz output clock 34 gnd 35 nc 36 aout1 output ecl - 100 mhz, 75 mhz or 50 mhz based on dsel(1:0) pins 37 aout0 output 38 nc 39 gnd 40 ecl+5v (same as vcc) 41 nc 42 nc 43 analo- g +5v 44 analo- g +5v 45 agnd 46 pcsel1 input programmable clock group c select 47 pcsel0 input 48 pbsel1 input programmable clock group b select 49 pbsel0 input 50 pasel1 input programmable clock group a select 51 pasel0 input 52 vc
3 ics9177 function tables example of system block diagram - clocking table 1: primary function table t ypical system usage table 2: clock select blocks function table note: x=a, b, or c. (see figure 1.) typical system usage ref in (mhx) dsel1# dsel0# rstl test f 1 out a out b out c out d description 25 0 0 1 0 200 mhz f /4 f /4 f /8 f /16 mode 0 - 1/1 25 0 1 1 0 300 mhz f /4 f /6 f /12 f /24 mode 1 - 3/2 331010 200/264 mhz f /2 f /4 f /8 f /16 mode 2 - 2/1 251110 x 1111mode 3 - a ll 1 -xx0x x 0000 reset mode - 0 0 1 1 tclk f /2 f /2 f /4 f/ 8 test mode 0 - 0 1 1 1 tclk f /2 f /3 f /6 f /12 test mode 1 - 1 0 1 1 tclk f/ 1 f /2 f /4 f /8 test mode 2 - 1 1 1 1 tclk f /2 f /2 f /2 f /2 test mode 3 pxsel 1 pxsel 0 function of clock select blocks 0 0 both outputs at the same frequency as out b . 0 1 both outputs at the same frequency as out c . 1 0 both outputs at the same frequency as out d . 1 1 both outputs disabled in the high state.
4 ics9177 note: the arrow indicates the point where the clock sequence starts to repeat. clock output timing diagrams 1:1 frequency ratio - mode 0 3:2 frequency ratio - mode 1 2:1 frequency ratio - mode 2
5 ics9177 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -.05v to vdd +.05v ambient operating temperature . . . . . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. ac/dc characteristics table 5: ac specification type out a.pecl pins (cpuclk) test load conditions: 100 w , 15 pf. note 1: the pecl levels are standard 10 khz positive ecl values as shown in the table above. note 2: pin skew and duty cycle are measured at the signal swing mid-point. note 3: the skew and duty cycle numbers reflect the recommended clock distribution method shown in figure 2 power supply specifications (total power consumption: approximately 750 mw) table 3: dc specifications ac/dc input specification table 4: ac specification of inputs note: tr and tf are typical values for input supply i(typ) i(max) v(min) v(typ) v(max) vdd 150 ma 200 ma 4.75v 5v 5.25v pin type vih(min) vil(max) tr tf all 2v 0.8v 3 3 parameter symbol test conditions min typ max units output high voltage 1 voh 3.87 4.67 volts output low voltage 1 vol 2.63 3.19 volts output high current ioh 38.7 46.7 ma output low current iol 26.3 31.9 ma rise time 10-90% tr 1 ns fall time 10-90% tf 1 ns duty cycle at 100 mhz 2, 3 dcyc 45 55 %
6 ics9177 table 6: ac specification type out b.ttl pins (50 mhz) test load conditions: 500 w , 15 pf. note 1: pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group. note 2: delay is the intrinsic delay between the ttl drivers switching and the pecl driver switching. this is measured from the outa.pecl signal at the signal swing mid-point to max output of the outb.ttl signals rising edge table 7: ac specification type out c.ttl pins (25 mhz) test load conditions: 500 w , 15 pf. note 1: pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group. note 2: spread is the absolute difference between the rising edge of any outc.ttl signal and the rising edge of any outb.ttl signal parameter symbol test conditions min typ max units output high voltage voh 2.4 3.2 5 volts output low voltage vol 0 0.3 0.8 volts output high current ioh 16 ma output low current iol 24 ma rise time 10-90% tr 1 2 3 ns fall time 10-90% tf 1 2 3 ns pin skew to other outb.ttl signals 1 tsk 250 500 ps duty cycle at 1.5v dcyc 45 55 % delay from outa.pecl signals 2 tdly .2 .5 ns skew associated with above delay 3 tdlyskw 0.5 ns parameter symbol test conditions min typ max units output high voltage voh 2.4 3.2 5 volts output low voltage vol 0 0.3 0.8 volts output high current ioh 16 ma output low current iol 24 ma rise time 10-90% tr 1 2 3 ns fall time 10-90% tf 1 2 3 ns pin skew to other outc.ttl signals 1 tsk 250 500 ps duty cycle at 1.5v dcyc 45 55 % spread to outb.ttl signals 2 tspb 500 ps
7 ics9177 table 8: ac specification type out d.ttl pins (12.5 mhz) test load conditions: 500w, 15 pf. note 1: delay is the intrinsic delay between the ttl drivers switching and the pecl driver switching. this is measured from the outa.pecl signal at the signal swing mid-point to max output of the outd.ttl signals rising edge parameter symbol test conditions min typ max units output high voltage voh 2.4 5 3.2 volts output low voltage vol 0 0.8 0.3 volts output high current ioh 16 ma output low current iol 24 ma rise time 10-90% tr 1 3 2 ns fall time 10-90% tf 1 3 2 ns pin skew to other outd.ttl signals tsk 500 250 ps duty cycle at 1.5v dcyc 45 55 % delay from outa.pecl signals 1 tdly .5 ns skew associated with above delay 2 tdlyskw 1.3 ns
8 ics9177 ordering information ics9177-01cf52 example: 52-pin qfp package ics xxxx-ppp m x#w lead count & package width lead count=1, 2 or 3 digits w=.3 soic or .6 dip; none=standard width package type f=qfp pattern number (2 or 3 digit number for parts with rom code patterns) device type (consists of 3 or 4 digit numbers) prefix ics, av=standard device; gsp=genlock lead count 44l 52l 64l 80l 100l 64l 80l 100l body thickness 2.0 2.70 footprint (body+) 3.20 dimensions tolerance a max. 2.45 3.40 a1 max. 0.25 0.25 d 0.25 13.20 17.20 17.20 d1 0.10 10.0 14.00 14.00 e 0.25 13.20 17.20 23.20 e1 0.10 10.0 14.00 20.00 l 0.15/-0.10 0.70 0.88 0.88 e basic 0.80 1.00 1.00 0.80 0.65 1.00 0.80 0.65 b +0.05 0.35 0.30 0.35 0.30 ccc max 0.10 0 - 7 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
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